发明名称 |
3D MEMORY WITH VERTICAL BIT LINES AND STAIRCASE WORD LINES AND VERTICAL SWITCHES AND METHODS THEREOF |
摘要 |
A vertical switching layer of a 3D memory device serves to switch a set of vertical local bit lines to a corresponding set of global bit lines, the vertical switching layer being a 2D array of TFT channels of vertical thin-film transistors (TFTs) aligned to connect to an array of local bit lines, each TFT switching a local bit line to a corresponding global bit line. The TFTs in the array have a separation of lengths Lx and Ly along the x- and y-axis respectively such that a gate material layer forms a surround gate around each TFT in an x-y plane and has a thickness that merges to form a row select line along the x-axis while maintaining a separation of length Ls between individual row select lines. The surround gate improves the switching capacity of the TFTs. |
申请公布号 |
KR20150030214(A) |
申请公布日期 |
2015.03.19 |
申请号 |
KR20147036711 |
申请日期 |
2013.06.04 |
申请人 |
SANDISK 3D LLC |
发明人 |
SCHEUERLEIN ROY E.;CERNEA RAUL ADRIAN |
分类号 |
G11C5/02;G11C7/18;G11C13/00;H01L27/105;H01L27/24;H01L45/00 |
主分类号 |
G11C5/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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