PHASE LOCKED LOOP AND METHOD FOR OPERATING THE SAME
摘要
The invention generally relates to phase locked loops (PLL), and more specifically to ultralow bandwidth phase locked loops. The invention may be for example embodied in an integrated circuit implementing a phase locked loop or a method for operating a phase locked loop. The invention provides a PLL with a control stage that uses only two storage cells, a counter and a digital-to-analog (DAC) converter. In comparison to prior-art PLLs using storage cells the configuration of the invention's control stage reduces the chip area required for the PLL reduced. The invention further suggests PVT compensation mechanisms for a PLL and implementing a PLL that has lower peaking in its frequency response, which results in better settling response.
申请公布号
WO2014120911(A8)
申请公布日期
2015.03.19
申请号
WO2014US13830
申请日期
2014.01.30
申请人
TEXAS INSTRUMENTS INCORPORATED;TEXAS INSTRUMENTS DEUTSCHLAND GMBH;TEXAS INSTRUMENTS JAPAN LIMITED