| 主权项 |
1. A ramp generator circuit comprising:
a reference signal generator circuit which generates a ramp waveform by outputting a step voltage signal in synchronization with a ramp driving clock having a frequency obtained by multiplying an input clock frequency by a predetermined power of 2 according to a value of a higher order bit of a gain control signal, the step voltage signal having a voltage variable by a fixed amount per unit time ranging from a predetermined start voltage to a predetermined end voltage; a clock control circuit which: (i) when a value of a gain control signal indicates a negative gain smaller than a standard gain, associates, one to one, fractional-N clocks as input clocks of the reference signal generator circuit with areas, and selectively outputs, as one of the input clocks of the reference signal generator circuit, one of the fractional-N clocks which is used in an associated one of the areas, the fractional-N clocks comprising 2̂m kinds of fractional-N clocks obtained by performing fractional-N frequency division on a frequency of a base clock according to 1/{2̂(m+1)−n} (an integer satisfying 0≦n<2̂m) and being associated with the areas in an ascending order of frequencies, the areas being obtained by dividing a code range of 2̂m (an integer satisfying m>0) represented by a lower order bit of the gain control signal and being associated with the input clocks in an ascending order of differences from a value of a gain control signal at a time when the standard gain is set; and (ii) when the value of the gain control signal indicates a positive gain larger than or equal to the standard gain, selectively outputs, as one of the input clocks of the reference signal generator circuit, a lowest-frequency fractional-N clock among the 2̂m kinds of fractional-N clocks; a standard voltage control circuit which outputs a standard voltage controlled to have a magnification equal to a period ratio between the one of the input clocks selectively output from the clock control circuit and an input clock of the reference signal generator circuit at the time when the standard gain is set; a variable gain circuit which: (i) controls amplitudes of ramp signals exponentially so that amplitude rates each defined by a ratio between a slope of a ramp signal in a case where the value of the gain control signal is a preset value of the standard gain and a slope of a ramp signal in a case where the value of the gain control signal is an arbitrarily set value of a gain become linear with respect to the value of the gain control signal; and (ii) sets the predetermined start voltage and the predetermined end voltage which define the ramp waveform which is of each of the areas so that (a) a period ratio between ramp driving clocks for adjacent ones of the areas and (b) a ratio between an amplitude of a ramp signal at the time when the standard gain is set and a largest amplitude of a ramp signal in each of the areas are equal to each other, when the value of the gain control signal indicates the negative gain after receiving the standard voltage output from the standard voltage control circuit; and an attenuator which is connected to a subsequent stage of the reference signal generator circuit, and outputs a ramp signal by attenuating the ramp waveform generated by the reference signal generator circuit. |
