PRE-FETCH IN A MULTI-STAGE MEMORY MANAGEMENT SYSTEM

摘要

A memory management system for managing a memory and includes a multi-stage memory management unit including control circuitry and cache memory. The cache memory may have a respective translation look-aside buffer for each stage of the multi-stage memory management unit. The control circuitry may be configured to generate a blank data request including a virtual address and information that specifies that data is not to be read from the memory, perform address translations based on the generated blank data request in multiple stages until a physical address is obtained, and discard the blank data request.

主权项

1. A memory management system for managing a memory, comprising:
a multi-stage memory management unit comprising control circuitry and cache memory; the cache memory comprising a respective translation look-aside buffer for each stage of the multi-stage memory management unit; wherein the control circuitry is configured to: generate a blank data request comprising a virtual address and information that specifies that data is not to be read from the memory, perform address translations based on the generated blank data request in multiple stages until a physical address is obtained, and discard the blank data request.