发明名称 SOLID-STATE IMAGING DEVICE AND CAMERA
摘要 The solid-state imaging device includes a D/A converting circuit generating a reference voltage to be used for an A/D conversion. The D/A converting circuit includes: a voltage generating circuit generating an analog voltage according to a digital signal; a buffer circuit (a resistor ladder upper voltage supplying buffer circuit) which buffers the generated analog voltage, the buffer circuit sampling and holding a bias voltage generated inside the buffer circuit, and outputting the buffered analog voltage using the held bias voltage; an analog signal outputting unit (a resistor ladder unit) outputting the reference voltage according to the inputted digital signal, by receiving an output from the buffer circuit; and a pre-charge amplifier which charges a noise-reducing capacitor in conjunction with the sampling and holding by the buffer circuit, the noise-reducing capacitor being connected to the analog signal outputting unit.
申请公布号 US2015077610(A1) 申请公布日期 2015.03.19
申请号 US201414554005 申请日期 2014.11.25
申请人 PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD. 发明人 SHISHIDO Sanshiro;HIGUCHI Masahiro
分类号 H04N5/374;H04N5/357;H04N5/3745;H04N5/378 主分类号 H04N5/374
代理机构 代理人
主权项 1. A solid-state imaging device comprising: a pixel unit having pixels arranged in a matrix, the pixels performing photoelectric conversion; a read-out circuit which reads out pixel signals from the pixel unit for each of groups of the pixels, and performs an analog-to-digital (A/D) conversion on the read pixel signals; and a digital-to-analog (D/A) converting circuit which generates a reference voltage to be used for the A/D conversion by the read-out circuit, the D/A converting circuit including: a voltage generating circuit which receives a bias voltage, and generates an analog voltage according to a value of an inputted digital signal;a buffer circuit which buffers the generated analog voltage, the buffer circuit sampling and holding a bias voltage generated inside the buffer circuit, and outputting the buffered analog voltage using the held bias voltage;an analog signal outputting unit configured to output the reference voltage by receiving an output from the buffer circuit and generating an output voltage according to the inputted digital signal; anda pre-charge circuit which charges a noise-reducing capacitor in conjunction with the sampling and holding, the noise-reducing capacitor being connected to the buffer circuit and the analog signal outputting unit.
地址 Osaka JP
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