发明名称 ループフィルタ
摘要 A loop filter include: a register that stores a result of arithmetic operation performed on a complex signal and outputs the stored complex signal; a first multiplier that multiplies the complex signal output from the register and a predetermined coefficient; an absolute value judging unit that outputs a multiplier coefficient used to control such that the amplitude of the complex signal output from the register is held in a predetermined range; a multiplier that multiplies an output from the first multiplier and the multiplier coefficient; a second multiplier that multiplies an input signal and a value (1−the predetermined coefficient); and an adder that adds an output from the multiplier to an output from the second multiplier and inputs a result of addition into the register.
申请公布号 JP5685908(B2) 申请公布日期 2015.03.18
申请号 JP20100265994 申请日期 2010.11.30
申请人 富士通株式会社 发明人 大友 尉央;小泉 伸和
分类号 H03H17/04;H03H17/00;H03H21/00;H04B10/07;H04B10/2507;H04B10/516;H04B10/556;H04B10/58;H04B10/61;H04L27/22 主分类号 H03H17/04
代理机构 代理人
主权项
地址