发明名称 キャッシュメモリの制御装置及びキャッシュメモリシステム
摘要 <p><P>PROBLEM TO BE SOLVED: To keep a use mode of cache memory as unchanged as possible before and after changing of address arrangement of main memory. <P>SOLUTION: A control device for cache memory controls the cache memory so that a program or data stored in addresses after a specific address in main memory is written in the address of the cache memory which is offset by a prescribed portion of addresses from the address of the cache memory specified based on a prescribed correspondence. The control device for cache memory comprises cache hit determination means determining a cache hit of the program or the data written in the address of the cache memory offset by the prescribed portion of addresses from the address of the cache memory specified based on the prescribed correspondence, when reading the program or the data stored in the addresses after the specific address in the main memory. <P>COPYRIGHT: (C)2012,JPO&INPIT</p>
申请公布号 JP5685963(B2) 申请公布日期 2015.03.18
申请号 JP20110021011 申请日期 2011.02.02
申请人 发明人
分类号 G06F12/08 主分类号 G06F12/08
代理机构 代理人
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