发明名称 Multi-valued on-die termination
摘要 An integrated circuit memory device stores a plurality of digital values that specify respective termination impedances. The memory device switchably couples respective sets of load elements to a data input/output (I/O) to apply the termination impedances specified by the digital values, including, applying a first termination impedance to the data I/O during an idle state of the memory device, applying a first one of two non-equal termination impedances to the data I/O while the memory device receives write data in a memory write operation and applying a second one of the two non-equal termination impedances to the data I/O while another memory device receives write data in a memory write operation. When outputting read data via the data I/O in a memory read operation, the memory device switchably couples to the data I/O at least a portion of the load elements included in the sets of load elements.
申请公布号 US8981811(B2) 申请公布日期 2015.03.17
申请号 US201313952393 申请日期 2013.07.26
申请人 Rambus Inc. 发明人 Oh Kyung Suk;Shaeffer Ian P.
分类号 H03K17/16;H03K19/0175;G06F13/40;G11C11/4093 主分类号 H03K17/16
代理机构 代理人 Shemwell Charles
主权项 1. A method of operation within an integrated circuit memory device, the method comprising: storing a plurality of digital values that specify respective termination impedances; switchably coupling sets of load elements to a data input/output (I/O) to apply termination impedances specified by the digital values, wherein switchably coupling the sets of load elements to the data I/O includes: applying a first termination impedance to the data I/O during an idle state of the memory device, andapplying one of two non-equal termination impedances to the data I/O, including applying a first one of the non-equal termination impedances to the data I/O while the memory device receives write data in a memory write operation and applying a second one of the non-equal termination impedances to the data I/O while another memory device receives write data in a memory write operation; and outputting read data via the data I/O in a memory read operation, wherein outputting read data includes switchably coupling to the data I/O at least a portion of the load elements included in the sets of load elements.
地址 Sunnyvale CA US