发明名称 High voltage three-dimensional devices having dielectric liners
摘要 High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric composed of a first dielectric layer disposed on the first fin active region, and a second, different, dielectric layer disposed on the first dielectric layer. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric composed of the second dielectric layer disposed on the second fin active region.
申请公布号 US8981481(B2) 申请公布日期 2015.03.17
申请号 US201213536732 申请日期 2012.06.28
申请人 Intel Corporation 发明人 Hafez Walid M.;Yeh Jeng-Ya D.;Tsai Curtis;Park Joodong;Jan Chia-Hong;Bhimarasetti Gopinath
分类号 H01L21/84;H01L27/12;H01L21/8234;H01L29/66 主分类号 H01L21/84
代理机构 Blakely, Sokoloff, Taylor & Zafman LLP 代理人 Blakely, Sokoloff, Taylor & Zafman LLP
主权项 1. A semiconductor structure, comprising: a first fin active region and a second fin active region disposed above a substrate; a first gate structure disposed above a top surface of, and along sidewalls of, the first fin active region, the first gate structure comprising a first gate dielectric, a first gate electrode, and first dielectric spacers, wherein the first gate dielectric comprises a first dielectric layer disposed on the first fin active region and along sidewalls of the first dielectric spacers and a second, different, dielectric layer disposed on the first dielectric layer and along the sidewalls of the first dielectric spacers; and a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region, the second gate structure comprising a second gate dielectric, a second gate electrode, and second dielectric spacers, wherein the second gate dielectric comprises the second dielectric layer disposed on the second fin active region and along sidewalls of the second dielectric spacers.
地址 Santa Clara CA US