| 发明名称 | Stacked structure, spin transistor, and reconfigurable logic circuit | ||
| 摘要 | A stacked structure according to an embodiment includes: a semiconductor layer; a first layer formed on the semiconductor layer, the first layer containing at least one element selected from Zr, Ti, and Hf, the first layer being not thinner than a monoatomic layer and not thicker than a pentatomic layer; a tunnel barrier layer formed on the first layer; and a magnetic layer formed on the tunnel barrier layer. | ||
| 申请公布号 | US8981436(B2) | 申请公布日期 | 2015.03.17 |
| 申请号 | US201314041055 | 申请日期 | 2013.09.30 |
| 申请人 | Kabushiki Kaisha Toshiba | 发明人 | Saito Yoshiaki;Inokuchi Tomoaki;Ishikawa Mizue;Sugiyama Hideyuki;Tanamoto Tetsufumi |
| 分类号 | H01L21/02;H01L27/108;H01L29/94;H01L29/82;H01L21/00;H01L43/10;H01L29/66;H03K19/173;H03K19/18;H03K19/177 | 主分类号 | H01L21/02 |
| 代理机构 | Oblon, McClelland, Maier & Neustadt, L.L.P. | 代理人 | Oblon, McClelland, Maier & Neustadt, L.L.P. |
| 主权项 | 1. A stacked structure comprising: a semiconductor layer; a first layer formed on the semiconductor layer, the first layer containing at least one element selected from Zr, Ti, and Hf, the first layer being not less than 1 atomic layer and not more than 5 atomic layers; a tunnel barrier layer formed on the first layer; and a magnetic layer formed on the tunnel barrier layer. | ||
| 地址 | Minato-ku JP | ||