System and method for reduction of bottom plate parasitic capacitance in charge pumps

摘要

A system for providing a load current at a specific output voltage to a circuit block of an integrated circuit (IC) includes a supply node at a supply voltage, a charge pump, and a cross-coupling circuit. The charge pump includes a first a first capacitor to charge while a first clock signal is high and a second capacitor to charge while a second clock signal is high. Each of the capacitors has a top plate node, a bottom plate node, a ground node, and an intermediate node between the bottom plate node and the ground node. The cross-coupling circuit couples the intermediate node of the first capacitor to the supply node while the second clock signal is high and couples the intermediate node of the second capacitor to the supply node while the first clock signal is high.

主权项

1. A system for providing a load current at a specific output voltage to a circuit block of an integrated circuit (IC), comprising:
a supply node at a supply voltage; a charge pump, comprising:
a first capacitor to charge while a first clock signal is high; anda second capacitor to charge while a second clock signal is high, each of the capacitors having a top plate node, a bottom plate node, a ground node, and an intermediate node between the bottom plate node and the ground node; and a cross-coupling circuit to:
couple the intermediate node of the first capacitor to the supply node while the second clock signal is high; andcouple the intermediate node of the second capacitor to the supply node while the first clock signal is high, wherein, for each capacitor, the top plate node comprises a gate of a MOS device, the bottom plate node comprises a source and a drain of the MOS device, the ground node comprises a P-substrate of the MOS device, and the intermediate node comprises an isolating N-well of the MOS device and wherein the cross-coupling circuit comprises: a first switch controlled by an isolating N-well voltage of the second capacitor that couples the isolating N-well of the first capacitor to the supply node; and a second switch controlled by an isolating N-well voltage of the first capacitor that couples the isolating N-well of the second capacitor to the supply node.