Memory array having improved radiation immunity

摘要

A memory array having improved radiation immunity is described. The memory array comprises a plurality of memory elements, each memory element having an p-type transistor formed in an n-type region; and a plurality of p-wells, each p-well having an n-type transistor coupled to a corresponding p-type transistor to form a memory element of the plurality of memory elements; wherein each p-well provides a p-n junction to dissipate minority charge in a portion of the n-type region occupied by a corresponding p-type transistor and associated with at least two adjacent memory elements. A method of implementing a memory array is also described.

主权项

1. A memory array having improved radiation immunity, comprising:
a plurality of memory elements; wherein each memory element has a pair of p-wells and an n-type region; wherein, for each memory element, each p-well has an n-type transistor coupled to a corresponding p-type transistor in the n-type region and is surrounded on at least three sides by the n-type region; and wherein, for each memory element, each p-well provides a p-n junction to dissipate minority charge in a portion of the n-type region occupied by a corresponding p-type transistor and associated with at least two adjacent memory elements.