发明名称 Processor with differential power analysis attack protection
摘要 A device including a processor to perform an operation yielding a result, the processor including a register including bit storage elements and including a first and second section, each element being operative to store a bit value, and a power consumption mask module to determine whether the whole result can be completely written in half or less than half of the register, determine a balancing entry if the result can be completely written in half or less than half of the register, a write module to perform a single write operation to the register including writing the result and the balancing entry to the first and second section, respectively, if the result can be completely written in half or less than half of the register else writing the result of the operation across at least part of the first and second section. Related apparatus and methods are also described.
申请公布号 US8984631(B2) 申请公布日期 2015.03.17
申请号 US201013521541 申请日期 2010.11.15
申请人 Cisco Technology Inc. 发明人 Kaluzhny Uri
分类号 G06F21/55;G06F21/75;G06F7/00;G06F21/14 主分类号 G06F21/55
代理机构 Husch Blackwell LLP 代理人 Husch Blackwell LLP
主权项 1. A device comprising a processor operative to perform an operation, the operation yielding a result, the processor including: a set of registers, each of the registers including a group of bit storage elements, each of the bit storage elements being operative to store a bit value of zero or one, one of the registers including a first section and a second section, the first section including a first plurality of the bit storage elements, the second section including a second plurality of the bit storage elements; a power consumption mask module to: determine whether (a) the whole result can be completely written in half, or less than half, of the one register or whether (b) the whole result needs to be written in more than half of the one register; and if the whole result can be completely written in half, or less than half, of the one register, determine a balancing entry to be written to the second section such that A plus B is equal to a predetermined masking number, wherein: A is the number of the bit storage elements of the second section where the bit value will be changed due to writing the balancing entry to the second section; andB is the number of the bit storage elements of the first section where the bit value will be changed due to writing the result of the operation to the first section; and a write module to perform a first single write operation to the one register including: (a) if the whole result can be completely written in half, or less than half, of the one register: writing the result of the operation to the first section of the one register; and writing the balancing entry to the second section of the one register, so that the total number of the bit storage elements of the one register changed during the first single write operation is equal to the predetermined masking number; and(b) if the whole result needs to be written in more than half of the one register, writing the result of the operation across at least part of the first section and at least part of the second section of the one register.
地址 San Jose CA US