Processing device with address translation probing and methods

摘要

A data processing device is provided that employs multiple translation look-aside buffers (TLBs) associated with respective processors that are configured to store selected address translations of a page table of a memory shared by the processors. The processing device is configured such that when an address translation is requested by a processor and is not found in the TLB associated with that processor, another TLB is probed for the requested address translation. The probe across to the other TLB may occur in advance of a walk of the page table for the requested address or alternatively a walk can be initiated concurrently with the probe. Where the probe successfully finds the requested address translation, the page table walk can be avoided or discontinued.

主权项

1. A data processing device comprising:
a first processing unit; a second processing unit; a page table of a memory shared by the first and second processing units; a first translation look-aside buffer (TLB) hierarchy configured to store selected address translations of the page table for use by the first processing unit; a second TLB hierarchy configured to store selected address translations of the page table for use by the second processing unit; the processing device configured to probe the second TLB hierarchy for an address translation requested by the first processing unit upon a condition that the requested address translation was not found in the first TLB hierarchy; and the processing device configured to probe the first TLB hierarchy for an address translation requested by the second processing unit upon a condition that the address translation requested by the second processing unit was not found in the second TLB hierarchy.