Receiver circuit and semiconductor integrated circuit

摘要

In a receiver circuit which can correct a deviation of phase between an input signal and a clock, a sampler detects an amplitude level of the input signal at timing indicated by the clock, a first comparison circuit compares a first and a second amplitude level detected by the sampler at first and second timings, respectively, with a determined threshold, an interpolation circuit calculates an intermediate level that approximates to an amplitude level of the input signal corresponding to an intermediate point between the first and second timings by an interpolation process based on the first and second amplitude levels, a second comparison circuit compares the intermediate level with the determined threshold, and a phase deviation detection circuit detects the deviation of phase between the clock and the input signal on the basis of comparison results obtained by the first and second comparison circuits.

主权项

1. A receiver circuit comprising:
a sampling circuit which detects an amplitude level of an input data signal at a sampling timing indicated by a sampling clock; a first comparison circuit which compares a first amplitude level and a second amplitude level detected by the sampling circuit at a first sampling timing and a second sampling timing, respectively, with a determined threshold; an interpolation circuit which calculates an intermediate level that approximates to an amplitude level of the input data signal corresponding to an intermediate point between the first sampling timing and the second sampling timing by an interpolation process based on the first amplitude level and the second amplitude level; a second comparison circuit which compares the intermediate level with the determined threshold; and a phase deviation detection circuit which detects a deviation of phase between the sampling clock and the input data signal on the basis of results of comparisons made by the first comparison circuit and the second comparison circuit.