Programmable delay circuitry

摘要

Programmable delay circuitry, which includes an input buffer circuit and variable delay circuitry, is disclosed. The variable delay circuitry includes an input stage, a correction start voltage circuit, and a variable delay capacitor. The input buffer circuit is coupled to the input stage, the correction start voltage circuit is coupled to the input stage, and the variable delay capacitor is coupled to the input stage. The programmable delay circuitry is configured to provide a fixed time delay and a variable time delay.

主权项

1. Programmable delay circuitry comprising:
an input buffer circuit coupled to an input stage; and variable delay circuitry comprising:
the input stage comprising a first P-type field effect transistor element (PFET) and a first N-type field effect transistor element (NFET), such that a drain of the first PFET and a drain of the first NFET are both coupled to a variable delay capacitor;a correction start voltage circuit coupled to the input stage; andthe variable delay capacitor coupled to the input stage, wherein the programmable delay circuitry is configured to provide a fixed time delay and a variable time delay.