发明名称 Phase-locked loop, method of operating the same, and devices having the same
摘要 A method of operating a phase-locked loop (PLL) such as an all-digital PLL includes operations of comparing a reference clock signal with a feedback signal of the PLL and outputting a comparison signal according to a result of the comparison, and detecting whether the PLL is in a lock state by using a number of times the comparison signal is toggled.
申请公布号 US8981824(B2) 申请公布日期 2015.03.17
申请号 US201414201285 申请日期 2014.03.07
申请人 Samsung Electronics Co., Ltd. 发明人 Park Jae Jin;Jang Tae Kwang;Liu Jenlung
分类号 H03L7/06;H03L7/10 主分类号 H03L7/06
代理机构 Sughrue Mion, PLLC 代理人 Sughrue Mion, PLLC
主权项 1. A method operating a phase-locked loop (PLL), the method comprising: comparing a reference clock signal with a feedback signal of the PLL, and outputting a comparison signal according to a result of the comparison; and detecting whether the PLL is in a lock state according to a number of times the comparison signal is toggled, wherein the detecting comprises comparing the number of times the comparison signal is toggled with a reference number of times, and detecting whether the PLL is in the lock state, according to the result of the comparison.
地址 Suwon-si KR