发明名称 |
Multiplying and adding matrices |
摘要 |
An apparatus and method are described for multiplying and adding matrices. For example, one embodiment of a method comprises decoding by a decoder in a processor device, a single instruction specifying an m-by-m matrix operation for a set of vectors, wherein each vector represents an m-by-m matrix of data elements and m is greater than one; issuing the single instruction for execution by an execution unit in the processor device; and responsive to the execution of the single instruction, generating a resultant vector, wherein the resultant vector represents an m-by-m matrix of data elements. |
申请公布号 |
US8984043(B2) |
申请公布日期 |
2015.03.17 |
申请号 |
US201012965657 |
申请日期 |
2010.12.10 |
申请人 |
Intel Corporation |
发明人 |
Ginzburg Boris;Rubanovich Simon;Eitan Benny |
分类号 |
G06F7/52;G06F17/16;G06F9/30 |
主分类号 |
G06F7/52 |
代理机构 |
Blakely, Sokoloff, Taylor & Zafman LLP |
代理人 |
Blakely, Sokoloff, Taylor & Zafman LLP |
主权项 |
1. A method comprising:
decoding by a decoder in a processor device, a single instruction specifying an m-by-m matrix operation for a set of vectors, wherein the set of vectors comprises a first vector, a second vector, and a third vector, wherein each vector represents an m-by-m matrix of data elements and m is greater than one, wherein the m-by-m matrix operation is a multiply-add operation; issuing the single instruction for execution by an execution unit in the processor device; and responsive to the execution of the single instruction, generating a fourth vector, wherein the fourth vector is stored separately from the first, second, and third vectors, wherein the fourth vector represents an m-by-m matrix of data elements, wherein the execution of the single instruction is performed by m sub-circuits, wherein each of the sub-circuits includes a plurality of multipliers and adders connected in a series, output of the last of the series connecting to a plurality of delay lines to generate respective portion of the fourth vector. |
地址 |
Santa Clara CA US |