发明名称 |
Circuit, control system, control method, and computer-readable recording medium for recording program |
摘要 |
In order to provide a circuit which can realize high-speed frequency tracking performance while satisfying jitter/wander suppression performance, the circuit controls loop gain of a PLL means, which extracts a clock signal of a SDH signal or an Ethernet signal from an OTN signal, on the basis of a result of processing a jitter/wander component and a frequency change state on the basis of phase comparison data of the PLL means. |
申请公布号 |
US8983016(B2) |
申请公布日期 |
2015.03.17 |
申请号 |
US201013257772 |
申请日期 |
2010.03.15 |
申请人 |
NEC Corporation |
发明人 |
Takahashi Masayuki;Yoshihara Tomoki |
分类号 |
H03B29/00;H03L7/085;H03L7/089;H03D3/24;H03L7/107;H03L7/093 |
主分类号 |
H03B29/00 |
代理机构 |
Sughrue Mion, PLLC |
代理人 |
Sughrue Mion, PLLC |
主权项 |
1. A circuit, comprising:
a control unit to control loop gain of a PLL (Phase Locked Loop) unit, which regenerates a clock signal of a SDH (Synchronous Digital Hierarchy) signal or an Ethernet signal from an OTN (Optical Transport Network) signal, on the basis of a result of processing a jitter/wander component and a frequency change state on the basis of phase comparison data of the PLL unit, wherein the control unit includes: a Jitter/Wander Detector unit which processes the jitter/wander component and creates jitter/wander information; a Frequency Change Slope Detector unit which processes the frequency change state and creates frequency change information; and a PLL Feed Forward Real-time Actuator unit which controls the loop gain of the PLL unit on the basis of the jitter/wander information and the frequency change information, and wherein the Jitter/Wander Detector unit carries out a dithering process to multiply the phase comparison data by n (n is predetermined number not smaller than two) , and to multiply the multiplied phase comparison data by 1/n after a FFT (Fast Fourier Transform) process. |
地址 |
Tokyo JP |