Chip package to support high-frequency processors

摘要

A chip package includes a processor, an interposer chip and a voltage regulator module (VRM). The interposer chip is electrically coupled to the processor by first electrical connectors proximate to a surface of the interposer chip. Moreover, the interposer chip includes second electrical connectors proximate to another surface of the interposer chip, which are electrically coupled to the first electrical connectors by through-substrate vias (TSVs) in the interposer chip. Note that the second electrical connectors can electrically couple the interposer chip to a circuit board. Furthermore, the VRM is electrically coupled to the processor by the interposer chip, and is proximate to the processor in the chip package, thereby reducing voltage droop. For example, the VRM may be electrically coupled to the surface of the interposer chip, and may be adjacent to the processor. Alternatively, the VRM may be electrically coupled to the other surface of the interposer chip.

主权项

1. A chip package, comprising:
a processor that includes multiple processor cores; an interposer chip electrically coupled to a first surface of the processor by first electrical connectors proximate to a first surface of the interposer chip, wherein the first electrical connectors are on top of the first surface of the interposer chip, wherein the interposer chip includes second electrical connectors proximate to a second surface of the interposer chip, wherein the interposer chip includes through-substrate vias (TSVs) electrically coupling the first electrical connectors to the second electrical connectors, wherein the second electrical connectors are configured to electrically couple the interposer chip to a circuit board, and wherein the processor is electrically coupled to the circuit board by using a first connector from the first electrical connectors, a second connector from the second electrical connectors, and a TSV in the TSVs that electrically connects the first connector to the second connector; and a voltage regulator module (VRM) electrically coupled to the processor by the interposer chip, wherein the VRM is proximate to the processor in the chip package, thereby reducing voltage droop, and wherein the VRM includes an array of VRMs, each VRM in the array configured to regulate power to a corresponding subset of the multiple processor cores independently from power regulation to processor cores of the multiple processor cores that are not in the corresponding subset.