DRAM sub-array level refresh

摘要

A memory controller coupled to a memory chip having a number of sub-arrays of memory cells is configured to determine a configuration of the memory chip. The memory controller is configured to read the sub-array configuration of the memory chip and to detect sub-array level conflicts between external commands and refresh operations. The memory controller keeps one or more non-conflicting pages open during the refresh operations.

主权项

1. A method of refreshing a dynamic random access memory (DRAM), comprising:
opening a page of the DRAM at a first row of a first DRAM bank of the DRAM, in which the first row of the first DRAM bank is in a first sub-array of the first DRAM bank; and refreshing a second row of the first DRAM bank before closing the first row of the first DRAM bank, in which the second row of the first DRAM bank is in a second sub-array of the first DRAM bank.