| 发明名称 | Wafer level chip scale package and process of manufacture | ||
| 摘要 | Power wafer level chip scale package (CSP) and process of manufacture are enclosed. The power wafer level chip scale package includes all source, gate and drain electrodes located on one side of the device, which is convenient for mounting to a printed circuit board (PCB) with solder paste. | ||
| 申请公布号 | US8981464(B2) | 申请公布日期 | 2015.03.17 |
| 申请号 | US201414271168 | 申请日期 | 2014.05.06 |
| 申请人 | Alpha and Omega Semiconductor Ltd | 发明人 | Feng Tao;Hébert François;Sun Ming;Ho Yueh-Se |
| 分类号 | H01L29/78;H01L29/49;H01L23/00;H01L29/06;H01L29/417;H01L29/45;H01L21/768;H01L23/48 | 主分类号 | H01L29/78 |
| 代理机构 | JDI Patent | 代理人 | Isenberg Joshua D.;JDI Patent |
| 主权项 | 1. A semiconductor device comprising: a semiconductor substrate having a first pad and a second pad respectively electrically connected to first and second regions located on a front side of the substrate; a first electrode electrically connected to the first pad; a second electrode electrically connected to the second pad; and a third electrode comprising a conductive layer on a side wall of a trimmed corner extending to the back side of the substrate, wherein the conductive layer is electrically connected to a third region located at a back side of the substrate. | ||
| 地址 | Hamilton BM | ||