| 主权项 |
1. An electrostatic discharge (ESD) protection structure comprising:
a semiconductor substrate including a first N-type well region and a first P-type well region, the first N-type well region including a first region and a second region, and the first P-type well region including a third region and a fourth region; a PMOS transistor located in the first region of the first N-type well region, the PMOS transistor including a gate located on the first N-type well region, and a source region and a drain region respectively located on both sides of the gate in the first N-type well region, the source region and the gate of the PMOS transistor being connected to a power supply terminal, and the drain region of the PMOS transistor being connected to an input and output (I/O) interface terminal; a first doped base region located in the second region of the first N-type well region, wherein the first doped base region is N-type doped and connected to an external trigger-voltage adjustment circuit, and wherein the external trigger-voltage adjustment circuit is configured to pull down an electric potential of the first doped base region when the power supply terminal generates an instantaneous electric potential difference; an NMOS transistor located in the third region of the first P-type well region, the NMOS transistor including a gate located on the first P-type well region, and a source region and a drain region respectively located on both sides of the gate in the first P-type well region, the drain region of the NMOS transistor being connected to the I/O interface terminal, and the gate and the source region of the NMOS transistor being connected to a ground terminal; a plurality of discretely-configured second doped base regions located in the fourth region of the first P-type well region, wherein the plurality of second doped base regions are P-type doped and are connected to the external trigger-voltage adjustment circuit, and wherein the external trigger-voltage adjustment circuit is configured to pull up an electric potential of the plurality of discretely-configured second doped base regions when the power supply terminal generates the instantaneous electric potential difference; a first N-region located in the fourth region of the first P-type well region, surrounding the plurality of discretely-configured second doped base regions, and connected to the I/O interface terminal; and a second N-region located in the fourth region of the first P-type well region, surrounding both the first N-region and the plurality of discretely-configured second doped base regions, and connected to the ground terminal. |
