Base, IC, and coupling interposer with boundary scan register

摘要

The disclosure describes a novel method and apparatus for improving interposers that connected stacked die assemblies to system substrates. The improvement includes the addition of IEEE 1149.1 circuitry within interposers to allow simplifying interconnect testing of digital and analog signal connections between the interposer and system substrate it is attached too. The improvement also includes the additional 1149.1 controlled circuitry that allows real time monitoring of voltage supply and ground buses in the interposer. The improvement also includes the additional of 1149.1 controlled circuitry that allows real time monitoring of functional digital and analog input and output signals in the interposer. The improvement also provides the ability to selectively serially link the 1149.1 circuitry in the interposer with 1149.1 circuitry in the die of the stack.

主权项

1. A device comprising:
A. a base substrate having functional input outputs, functional output inputs, a test data in output, a test mode select output, a test clock output, and a test data out input; B. an integrated circuit die having functional inputs and functional outputs, and having no connection to any of the test data in output, the test mode select output, the test clock output, and the test data out input; and C. an interposer, including:
i. first functional input pads coupled to the functional input outputs of the base substrate;ii. first functional output pads coupled to the functional output inputs of the base substrate;iii. second functional input pads coupled to the functional inputs of the integrated circuit die;iv. second functional output pads coupled to the functional outputs of the integrated circuit die;v. a test access port controller coupled to the test clock output and the test mode select output, and having a control output bus; andvi. boundary register circuitry including boundary scan cells connected in series and coupled between the test data in output and the test data out input, and having a control input connected to the control output bus of the test access port controller, and the boundary register circuitry selectively coupling the first functional input pads to the second functional input pads and selectively coupling the second functional output pads to the first functional output pads.