| 摘要 |
本发明提出一种暂态电压抑制元件及其制造方法，暂态电压抑制元件包含：导电层；半导体基板，形成于导电层上，具有P型导电型；埋层，形成于半导体基板上，具有N型导电型；轻掺杂层，形成于埋层上，具有P型导电型；覆盖区，形成于轻掺杂层上，具有P型导电型；以及反向区，形成于覆盖区上，具有N型导电型；其中，齐纳(Zener)二极体包括反向区与覆盖区，NPN双极接面电晶体(bipolar iunction transistor,BJT)包括反向区、覆盖区、轻掺杂层与埋层。; a semiconductor substrate with a P conductive type, which is formed on the conductive layer; a buried layer with an N conductive type, which is formed on the semiconductor substrate; a lightly doped layer with the P conductive type, which is formed on the buried layer; a cap region with the P conductive type, which is formed on the lightly doped layer; and a reverse region with the N conductive type, which is formed on the cap region; wherein a Zener diode includes the reverse region and the cap region, and an NPN bipolar junction transistor (BJT) includes the reverse region, the cap region, the lightly doped layer, and the buried layer. |
