发明名称 DESIGN METHOD AND PROGRAM FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To suppress power consumption within a range satisfying timing constraints.SOLUTION: A design device determines wiring lines L1-1 to L1-n for transmission of signals and wiring lines L2-1 to L2-n not used for transmission of the signals, out of a plurality of wiring lines L1-1 to L1-n and L2-1 to L2-n of a semiconductor integrated circuit 1. The design device determines to use the wiring lines L2-1 to L2-n as charge storage wiring lines for reusing the charges of the wiring lines L1-1 to L1-n in the largest number of wiring lines L1-1 to L1-n within a range satisfying timing constraints on the basis of the operation rates of the signals, which are transmitted to the wiring lines L1-1 to L1-n, and delay times of the wiring lines L1-1 to L1-n.</p>
申请公布号 JP2015049610(A) 申请公布日期 2015.03.16
申请号 JP20130179746 申请日期 2013.08.30
申请人 FUJITSU LTD 发明人 TAMURA YASUTAKA;JASON ANDERSON;SAFEEN HUDA;FUJIMOTO HIROAKI
分类号 G06F17/50;H01L21/82;H01L21/822;H01L27/04 主分类号 G06F17/50
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