LINK AGGREGATOR FOR AN ELECTRONIC DISPLAY

摘要

Video data and auxiliary data may be sent between a processor and a display device via a single cable using a link aggregator. As such, the link aggregator may receive a first parallel signal that may include the video data and a second parallel signal that may include auxiliary data from the processor. The link aggregator may then send the first parallel signal and the second parallel signal as an aggregated signal to the display device. Upon receiving the aggregated signal at the display device, the link aggregator may de-aggregate the aggregated signal into the first parallel signal and the second parallel signal. The link aggregator may then send the first parallel signal and the second parallel signal to a timing controller of the display device, such that the timing controller may display the video data using the display device.

主权项

1. A display port aggregator, comprising:
a transmitter component configured to:
receive a first parallel signal comprising video data and a second parallel signal comprising auxiliary data from a processor, wherein the video data comprises one or more images to be displayed on a display device;aggregate the first parallel signal and the second parallel signal, thereby generating a serial signal; andtransmit the serial signal via a single cable to the display device; and a receiver component configured to:
receive the serial signal from the transmitter component via the single cable;de-aggregate the serial signal to obtain the first parallel signal and the second parallel signal; andsend the first parallel signal and the second parallel signal to a timing controller of the display device, wherein the timing controller is configured to display the images on the display device.