CONTROL TEST POINT FOR TIMING STABILITY DURING SCAN CAPTURE

摘要

A scan chain of an integrated circuit is disclosed, including a plurality of scannable storage elements and a control test point having a scan latch and an integrated clock gate (ICG) with clock, functional enable (FE) and scan enable (SE) inputs, and a gated clock output. The ICG may respond to an SE input active state, in a serial scan mode allowing the gated clock output to change. The ICG may also be operated in a scan capture mode, responding to an SE input inactive state, in which the gated clock output is inhibited from changing in response to a low FE input level. The ICG's gated clock output may be coupled to the scan latch clock input, which may hold its data output at a fixed level in response to ICG's gated clock output being inhibited from changing during the scan capture operation.

主权项

1. A scan chain of an integrated circuit (IC) comprising:
a plurality of scannable storage elements designed to receive an output state of combinational logic during a scan capture operation; and a control test point (CTP) including:
a first integrated clock gate (ICG) having a clock input, a gated clock output, a functional enable (FE) input, and a first scan enable (SE) input, the first ICG configured to operate:
in response to an active state of the first SE input, in a serial scan mode that allows the gated clock output to change in response to data received by the first SE input during a serial scan operation, andin response to an inactive state of the first SE input, in a scan capture mode in which the gated clock output is inhibited from changing during the scan capture operation in response to the FE input being held at a low logic level; anda scan latch having a clock input coupled to the gated clock output of the first ICG and a data output, the scan latch configured to hold the data output at a fixed logic level in response to the gated clock output of the first ICG being inhibited from changing during the scan capture operation.