| 发明名称 |
SEMICONDUCTOR MEMORY DEVICE |
| 摘要 |
A semiconductor memory device according to an embodiment is provided with a plurality of first latch circuits that latch setting-data at different timings, a plurality of hold circuits provided corresponding to the respective plurality of first latch circuits, each holding data latched by the corresponding first latch circuit, and an address decoder that decodes an address that specifies a destination to hold data. Each of the plurality of hold circuits has one or more holding parts that hold data latched by the corresponding first latch circuit based on a decode signal decoded by the address decoder. |
| 申请公布号 |
US2015071001(A1) |
申请公布日期 |
2015.03.12 |
| 申请号 |
US201414204565 |
申请日期 |
2014.03.11 |
| 申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
KANAGAWA Naoaki |
| 分类号 |
G11C7/10;G11C16/06 |
主分类号 |
G11C7/10 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A semiconductor memory device comprising:
a plurality of first latch circuits latching setting-data at different timings; a plurality of hold circuits, provided corresponding to the respective plurality of first latch circuits, each holding data latched by the corresponding first latch circuit; and an address decoder decoding an address that specifies a destination to hold the data, wherein each of the plurality of hold circuits has one or more holding parts that hold data latched by the corresponding first latch circuit based on a decode signal decoded by the address decoder. |
| 地址 |
MINATO-KU JP |
