System and Method for an Asynchronous Processor with Token-Based Very Long Instruction Word Architecture

摘要

Embodiments are provided for an asynchronous processor with token-based very long instruction word architecture. The asynchronous processor comprises a memory configured to cache a plurality of instructions, a feedback engine configured to receive the instructions in bundles of instructions at a time (referred to as very long instruction word) and to decode the instructions, and a crossbar bus configured to transfer calculation information and results of the asynchronous processor. The apparatus further comprises a plurality of sets of execution units (XUs) between the feedback engine and the crossbar bus. Each set of the sets of XUs comprises a plurality of XUs arranged in series and configured to process a bundle of instructions received at the each set from the feedback engine.

主权项

1. A method performed by an asynchronous processor, the method comprising:
issuing a plurality of instruction bundles from a feedback engine to a plurality of corresponding bundle registers (BRs) associated with a plurality of sets of arithmetic and logic units (ALUs) in the asynchronous processor; processing, in the ALUs in each set of the sets of ALUs, a plurality of instructions in an instruction bundle received, from the feedback engine, in a corresponding BR associated with the each set; and accessing, by the ALUs in the each set, resources for processing the instructions using gating and passing of a plurality of tokens.