MEMORY TRANSACTION ORDERING

摘要

Embodiments are disclosed relating to methods of ordering transactions across a bus of a computing device. One embodiment of a method includes determining a current target memory channel for an incoming transaction request, and passing the incoming transaction request downstream if the current target memory channel matches an outstanding target memory channel indicated by a direction bit of a counter or the counter equals zero. The method further includes holding the incoming transaction request if the counter is greater than zero and the current target memory channel does not match the outstanding target memory channel.

主权项

1. A method of ordering transactions across a bus of a computing device, the method comprising:
determining a current target memory channel for an incoming transaction request; passing the incoming transaction request downstream if
(a) the current target memory channel matches an outstanding target memory channel indicated by a direction bit of a counter identifying a number of outstanding requests or(b) the counter identifying the number of outstanding requests equals zero; and holding the incoming transaction request if the counter is greater than zero and the current target memory channel does not match the outstanding target memory channel.