| 摘要 |
<p>Disclosed is a NOR flash memory device reducing a program noise. The NOR flash memory device of the present invention includes: a memory array including multiple flash memory cells placed on a matrix structure formed of multiple word lines and cell bit lines sequentially arranged; a column selection circuit operated to select a word line according to a column address; a row selection circuit operated to select a cell bit line according to a row address; a program driving circuit operated to provide a program operation voltage to the selected cell bit line in a program section to activate a program operation signal; and a program verification circuit verifying whether the flash memory cells, to which the program operation signal is applied in the program section, succeeds in programming, in a verification section to activate a verification operation signal. At this point, the program operation voltage increases step by step. According to the NOR flash memory device of the present invention, a coupling noise with program prohibition bit lines, adjacent to a program bit line, is reduced and as a result, the whole program noise is reduced so that the malfunction of the program is significantly reduced.</p> |
