发明名称 3DIC Interconnect Apparatus and Method
摘要 An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.
申请公布号 US2015069619(A1) 申请公布日期 2015.03.12
申请号 US201314020370 申请日期 2013.09.06
申请人 Taiwan Semiconductor Manufacturing Company, Ltd. 发明人 Chou Shih Pei;Hsu Hung-Wen;Su Ching-Chung;Tsao Chun-Han;Chia-Chieh Lin;Tsai Shu-Ting;Lu Jiech-Fun;Liu Shih-Chang;Tu Yeur-Luen;Tsai Chia-Shiung
分类号 H01L23/48;H01L25/065;H01L25/00 主分类号 H01L23/48
代理机构 代理人
主权项 1. An apparatus comprising: a first semiconductor chip comprising a first substrate, a plurality of first inter-metal dielectric layers and a plurality of first metal lines formed in the first inter-metal dielectric layers over the first substrate; a second semiconductor chip having a surface bonded to a first surface of the first semiconductor chip, wherein the second semiconductor chip comprises a second substrate, a plurality of second inter-metal dielectric layers and a plurality of second metal lines formed in the second inter-metal dielectric layers over the second substrate; and a conductive plug extending from a second surface of the first semiconductor chip, through the first semiconductor chip, and to one of the plurality of second metal lines in the second semiconductor chip, the conductive plug having a continuous vertical sidewall from the second surface of the first semiconductor chip to one of the plurality of metal lines in the first semiconductor chip.
地址 Hsin-Chu TW
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