METHODS OF FORMING FINFET SEMICONDUCTOR DEVICES WITH SELF-ALIGNED CONTACT ELEMENTS USING A REPLACEMENT GATE PROCESS AND THE RESULTING DEVICES

摘要

One method disclosed herein includes removing a sacrificial gate structure and forming a replacement gate structure in its place, after forming the replacement gate structure, forming a metal silicide layer on an entire upper surface area of each of a plurality of source/drain regions and, with the replacement gate structure in position, forming at least one source/drain contact structure for each of the plurality of source/drain regions, wherein the at least one source/drain contact structure is conductively coupled to a portion of the metal silicide layer and a dimension of the at least one source/drain contact structure in a gate width direction of the transistor is less than a dimension of the source/drain region in the gate width direction.

主权项

1. A method of forming a FinFET transistor above an active region defined in a semiconductor substrate, said transistor comprising a plurality of fins, wherein the method comprises:
forming a sacrificial gate structure above said plurality of fins of said FinFET transistor; forming a sidewall spacer adjacent said sacrificial gate structure; performing an epitaxial deposition fin-merger process to form a plurality of merged-fin regions that define a plurality of source/drain regions for said transistor; removing said sacrificial gate structure and forming a replacement gate structure in its place; at some point after forming said replacement gate structure, forming a metal silicide layer on an entire upper surface area of each of said plurality of source/drain regions; and with said replacement gate structure in position, forming at least one source/drain contact structure for each of said plurality of source/drain regions, wherein said at least one source/drain contact structure is formed such that it is conductively coupled to a portion of said metal silicide layer and a dimension of said at least one source/drain contact structure in a gate width direction of said transistor is less than a dimension of said source/drain region in said gate width direction.