System and Method for an Asynchronous Processor with Multiple Threading

摘要

Embodiments are provided for an asynchronous processor with multiple threading. The asynchronous processor includes a program counter (PC) logic and instruction cache unit comprising a plurality of PC logics configured to perform branch prediction and loop predication for a plurality of threads of instructions, and determine target PC addresses for caching the plurality of threads. The processor further comprises an instruction memory configured to cache the plurality of threads in accordance with the target PC addresses from the PC logic and instruction cache unit. The processor further includes a multi-threading (MT) scheduling unit configured to schedule and merge instruction flows for the plurality of threads from the instruction memory into a single combined thread of instructions. Additionally, a MT register window register is included to map operands in the plurality of threads to a plurality of corresponding register windows in a register file.

主权项

1. A method performed by an asynchronous processor, the method comprising:
receiving a plurality of threads of instructions from an execution unit of the asynchronous processor; initiating, for the plurality of threads of instructions, a plurality of corresponding program counter (PC) logics at a PC logic and instruction cache unit of the asynchronous processor; performing, using each one of the PC logics, branch prediction and loop predication for one corresponding thread of the plurality of threads of instructions; determining, using each one of the PC logics, a target PC address for the one corresponding thread; and caching the one corresponding thread in an instruction memory in accordance with the target PC address.