System and Method for an Asynchronous Processor with Pepelined Arithmetic and Logic Unit

摘要

Embodiments are provided for an asynchronous processor with pipelined arithmetic and logic unit. The asynchronous processor includes a non-transitory memory for storing instructions and a plurality of instruction execution units (XUs) arranged in a ring architecture for passing tokens. Each one of the XUs comprises a logic circuit configured to fetch a first instruction from the non-transitory memory, and execute the first instruction. The logic circuit is also configured to fetch a second instruction from the non-transitory memory, and execute the second instruction, regardless whether the one of the XUs holds a token for writing the first instruction. The logic circuit is further configured to write the first instruction to the non-transitory memory after fetching the second instruction.

主权项

1. A method performed by an asynchronous processor, the method comprising:
fetching, at an instruction execution unit (XU) of the asynchronous processor, a first instruction; executing the first instruction in the XU; upon holding, at the XU, a token for fetching a next instruction, fetching a second instruction; and upon holding, at the XU, a token for launching the next instruction, executing the second instruction.