TRANSISTOR FABRICATION TECHNIQUE INCLUDING SACRIFICIAL PROTECTIVE LAYER FOR SOURCE/DRAIN AT CONTACT LOCATION

摘要

Techniques are disclosed for transistor fabrication including a sacrificial protective layer for source/drain (S/D) regions to minimize contact resistance. The sacrificial protective layer may be selectively deposited on S/D regions after such regions have been formed, but prior to the deposition of an insulator layer on the S/D regions. Subsequently, after contact trench etch is performed, an additional etch process may be performed to remove the sacrificial protective layer and expose a clean S/D surface. Thus, the sacrificial protective layer can protect the contact locations of the S/D regions from contamination (e.g., oxidation or nitridation) caused by insulator layer deposition. The sacrificial protective layer can also protect the S/D regions from undesired insulator material remaining on the S/D contact surface, particularly for non-planar transistor structures (e.g., finned or nanowire/nanoribbon transistor structures).

主权项

1. A semiconductor device, comprising:
a substrate having a number of channel regions; source/drain regions on the substrate and adjacent to a corresponding channel region; a gate region above each channel region and between the source/drain regions; a sacrificial protective layer on a portion of the source/drain regions; at least one insulator layer over the sacrificial protective layer; trench contact areas in the source/drain regions, wherein the sacrificial protective layer is absent from the trench contact areas; and at least one contact layer in the trench contact areas of the source/drain regions.