| 主权项 |
1. A method of manufacturing a silicon carbide semiconductor device for forming a JFET in a cell region of a semiconductor substrate, and forming a first concave portion that configures a first mesa portion in an outer periphery of the cell region, and a second concave portion that configures a second mesa portion in an outer peripheral position of the cell region than a stepped portion of the first mesa portion within the first concave portion, the method comprising:
preparing the semiconductor substrate including a first conductivity type substrate made of silicon carbide, a drift layer of a first conductivity type formed on the first conductivity type substrate by epitaxial growth, a first gate region of a second conductivity type formed on the drift layer by epitaxial growth, and a source region of the first conductivity type formed on the first gate region by epitaxial growth or ion implantation; forming a strip-like trench that penetrates through the source region and the first gate region, and reaches the drift layer with one direction as a longitudinal direction; forming a channel layer of the first conductivity type on an inner wall of the trench by epitaxial growth; forming a second conductivity type second gate region on the channel layer by epitaxial growth; planarizing the channel layer and the second gate region to expose the source region; after the planarizing, forming the second concave portion having a depth deeper than the source region, and as deep as a boundary portion between the source region and the first gate region is exposed, in an outer peripheral region surrounding a cell region, with a region in which the trench is formed as the cell region in which the JFET is configured, by conducting selective etching; after forming the second concave portion, detecting a thickness of the source region by observing a pn junction between the source region and the first gate region exposed by the second concave portion, conducting selective etching on the basis of the detection result to form the first concave portion deeper than the thickness of the source region inside of the outer peripheral region in an outer periphery of the cell region, and to make the second concave portion deeper than the second gate region; after forming an interlayer insulating film on surfaces of the second gate region, the channel region, and the source region, forming contact holes in the interlayer insulating film, and forming a gate electrode connected to at least one of the first gate region and the second gate region, and a source electrode connected to the source region through the contact holes; and forming a drain electrode on a rear surface of the first conductivity type substrate. |
