NANOWIRE COMPATIBLE E-FUSE

摘要

An e-fuse is provided in one area of a semiconductor substrate. The E-fuse includes a vertical stack of from, bottom to top, base metal semiconductor alloy portion, a first metal semiconductor alloy portion, a second metal semiconductor portion, a third metal semiconductor alloy portion and a fourth metal semiconductor alloy portion, wherein the first metal semiconductor alloy portion and the third metal semiconductor portion have outer edges that are vertically offset and do not extend beyond vertical edges of the second metal semiconductor alloy portion and the fourth metal semiconductor alloy portion.

主权项

1. A method of forming a semiconductor structure comprising:
forming a multilayered epitaxial semiconductor material stack of, from bottom to top, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer and a fourth semiconductor layer on an uppermost surface of a semiconductor substrate; patterning said multilayered epitaxial semiconductor material stack into a first patterned material stack containing, from bottom to top, a first semiconductor portion, a second semiconductor portion, a third semiconductor portion and a fourth semiconductor portion; forming an isolation structure on each exposed portion of said semiconductor substrate and at a footprint of said first patterned material stack; performing a lateral etch in which a width of exposed portions of said first semiconductor portion of said first patterned material stack and a width of said third semiconductor portion of said first patterned material stack are narrowed, while maintaining a width of said second semiconductor portion and a width of said fourth semiconductor portion; and converting said etched first semiconductor portion into a first metal semiconductor alloy portion, said second semiconductor portion into a second metal semiconductor alloy portion, said etched third semiconductor alloy portion into a third metal semiconductor alloy portion and said fourth semiconductor portion into a fourth metal semiconductor alloy portion, wherein outer edges of said first and third metal semiconductor alloy portions are vertically offset and do not extend beyond outer edges of said second and fourth metal semiconductor alloy portions.