| 摘要 |
The invention relates to a processor for processing digital data (80), which comprises at least one butterfly operator (82) configurable between a first configuration in which the butterfly operator performs a Fast Fourier transform computation and a second configuration in which the butterfly operator performs a computation of the metrics of an implementation of a channel decoding algorithm. Said butterfly operator has an architecture comprising the hardware adder/subtractor modules (40', 42', 48', 50'), each including a plurality of basic adder/subtractor modules. Said hardware adder/subtractor modules (40', 42', 48', 50') are configurable by means of at least one programmable parameter (cmd) for the selection of an addition/subtraction dynamic range among a plurality of possible addition/subtraction dynamic range between a maximum dynamic range according to which a single addition/subtraction computation at maximum size of the operands is performed by all of the basic modules in a cascade and a minimum dynamic range according to which a plurality of independent addition/subtraction computations at minimum size of the operands are performed by each one of the basic modules in parallel. |
