发明名称 PLL回路
摘要 A PLL circuit, has a phase comparator for comparing phases of a reference clock and a feedback clock, and outputting a phase comparison signal indicating the phase difference; a charge pump circuit, which, during a time period corresponding to the phase difference, outputs a first charge pump current and a second charge pump current; a loop filter, having a capacitor storing electric charge based on the first and second charge pump currents, which generates a control voltage due to stored electric charge; an oscillator generating an output clock at a frequency according to the control voltage; a frequency divider frequency-dividing the output clock and outputs the feedback clock; and a charge pump adjustment circuit, which, when in a locked state, adjusts current quantity of the first or the second charge pump current such that the phase difference is suppressed, according to the phase difference indicated by the phase comparison signal.
申请公布号 JP5682281(B2) 申请公布日期 2015.03.11
申请号 JP20100279341 申请日期 2010.12.15
申请人 发明人
分类号 H03L7/093;H03L7/08 主分类号 H03L7/093
代理机构 代理人
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