| 摘要 |
<p>A miniaturized non-linear conversion unit is achieved. Included is an encryption processing part configured to divide and input configuration bits of data to be processed into a plurality of lines, and to repeatedly execute a data conversion processing applying a round function as to the data in each line, wherein the encryption processing part includes an F function executing unit configured to input one line of data configuring the plurality of lines, and to generate conversion data, wherein the F function executing unit includes a non-linear conversion processing unit configured to execute a non-linear conversion processing, and wherein the non-linear conversion processing unit includes a repeating structure of a non-linear calculation unit made up from either one NAND or NOR, and either one XOR or XNOR calculation unit, and a bit replacement unit. The miniaturized non-linear conversion unit is achieved by this repeating configuration.</p> |
