Apparatus and method to adjust clock duty cycle of memory

摘要

An embodiment of the invention provides a memory controller for controlling a memory. The memory controller comprises a pulse width modulation module, a voltage comparator and a duty cycle calibration device. The pulse width modulation module is suitable for receiving a clock signal to generate a first voltage. The voltage comparator is suitable for receiving and comparing a reference voltage with the first voltage to output a comparison signal. The duty cycle calibration device is suitable for adjusting a duty cycle of the clock signal according to the comparison signal.

主权项

1. A memory controller for controlling a memory, comprising:
a pulse width modulation module suitable for receiving a clock signal to generate a first voltage; a voltage comparator suitable for receiving and comparing a reference voltage with the first voltage to output a comparison signal; and a duty cycle calibration device suitable for adjusting a duty cycle of the clock signal according to the comparison signal; wherein the duty cycle calibration device comprises a duty cycle corrector suitable for generating a duty cycle calibration signal according to the comparison signal, and wherein the duty cycle calibration signal comprises a phase signal that represents a duty cycle calibration amount, and a select signal which indicates that the duty cycle of the clock signal is larger than or less than a target duty cycle.