发明名称 Resistive memory architectures with multiple memory cells per access device
摘要 A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices.
申请公布号 US8976562(B2) 申请公布日期 2015.03.10
申请号 US201113292884 申请日期 2011.11.09
申请人 发明人 Liu Jun;Violette Mike
分类号 G11C5/06;G11C13/00;H01L27/24;H01L45/00 主分类号 G11C5/06
代理机构 Dickstein Shapiro LLP 代理人 Dickstein Shapiro LLP
主权项 1. A resistive memory structure, comprising: a plurality of stacked resistive memory cells, each stack including a first and a second resistive memory cell; a common electrode positioned between the first and second resistive memory cells of a stack and electrically coupling the first and second resistive memory cells to a cell select line; and a plurality of access devices, each access device electrically coupled to a first resistive memory cell of a first stack via a first rectifying device and to a second resistive memory of a second stack via a second rectifying device.
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