Reversing processing order in half-pumped SIMD execution units to achieve K cycle issue-to-issue latency

摘要

Techniques for reducing issue-to-issue latency by reversing processing order in half-pumped single instruction multiple data (SIMD) execution units are described. In one embodiment a processor functional unit is provided comprising a frontend unit, and execution core unit, a backend unit, an execution order control signal unit, a first interconnect coupled between and output and an input of the execution core unit and a second interconnect coupled between an output of the backend unit and an input of the frontend unit. In operation, the execution order control signal unit generates a forwarding order control signal based on the parity of an applied clock signal on reception of a first vector instruction. This control signal is in turn used to selectively forward first and second portions of an execution result of the first vector instruction via the interconnects for use in the execution of a dependent second vector instruction.

主权项

1. A method comprising:
receiving a plurality of instructions, wherein
said plurality of instructions comprises a first vector instruction and a second vector instruction, andexecution of said second vector instruction depends on an execution result of said first vector instruction, executing said first vector instruction utilizing a processor functional unit, wherein said processor functional unit comprises a pipelined execution unit; determining a forwarding order of a first portion of said execution result and a second portion of said execution result in dependence on a parity of a clock signal applied to said processor functional unit at the time said first vector instruction was received, wherein said determining comprises determining said forwarding order utilizing a single-bit binary counter to identify said parity of said clock signal upon receipt of said first vector instruction; and forwarding said first portion of said execution result and said second portion of said execution result from an output coupled to said pipelined execution unit to an input coupled to said pipelined execution unit according to said forwarding order, wherein said forwarding comprises:
forwarding said first portion of said execution result prior to forwarding said second portion of said execution result in response to a determination that said parity of said clock signal upon said receipt of said first vector instruction is even, andforwarding said second portion of said execution result prior to forwarding said first portion of said execution result in response to a determination that said parity of said clock signal upon receipt of said first vector instruction is odd.