发明名称 |
Compact level shifter |
摘要 |
Embodiments of the present invention provide a device for level shifting an input signal. The device includes an output buffer that has: an output node, a p-FET coupled to a high reference voltage, and an n-FET coupled to a low reference voltage. The device also includes two latches. The first latch has a first latch output that drives a gate of the p-FET via an inverting circuit element. The second latch has a second latch output that drives a gate of the n-FET via a non-inverting circuit element. The device also includes a reset signal pulse generator that receives the input signal and generates a reset signal pulse in response to a transition in the input signal. Both of the latches are placed in a reset state by the reset signal pulse. |
申请公布号 |
US8975943(B2) |
申请公布日期 |
2015.03.10 |
申请号 |
US201313904941 |
申请日期 |
2013.05.29 |
申请人 |
Silanna Semiconductor U.S.A., Inc. |
发明人 |
Lou Perry |
分类号 |
H03L5/00;H03K19/0175 |
主分类号 |
H03L5/00 |
代理机构 |
The Mueller Law Office, P.C. |
代理人 |
The Mueller Law Office, P.C. |
主权项 |
1. A device for level shifting an input signal comprising:
an output buffer having an output node, a p-type field effect transistor coupled to a high reference voltage, and an n-type field effect transistor coupled to a low reference voltage; a first latch having a first latch output, said first latch output driving a gate of said p-type field effect transistor via an inverting circuit element; a second latch having a second latch output, said second latch output driving a gate of said n-type field effect transistor; and a reset signal pulse generator receiving said input signal and generating a reset signal pulse in response to: (1) a transition in said input signal from a high input voltage to a low input voltage, and (2) a transition in said input signal from said low input voltage to said high input voltage; wherein both said first and said second latches are placed in a reset state by said reset signal pulse. |
地址 |
San Diego CA US |