Semiconductor device and method of manufacturing the same

摘要

In an LCD driver, in a high voltage resistant MISFET, end portions of a gate electrode run onto electric field relaxing insulation regions. Wires to become source wires or drain wires are formed on an interlayer insulation film of the first layer over the high voltage resistant MISFET. At this moment, when a distance from an interface between a semiconductor substrate and a gate insulation film to an upper portion of the gate electrode is defined as “a”, and a distance from the upper portion of the gate electrode to an upper portion of the interlayer insulation film on which the wires are formed is defined as “b”, a relation of a>b is established. In such a high voltage resistant MISFET structured in this manner, the wires are arranged so as not to be overlapped planarly with the gate electrode of the high voltage resistant MISFET.

主权项

1. A method for manufacturing a semiconductor device, comprising steps of:
(a) forming a gate insulation film over a semiconductor substrate; (b) forming a gate electrode over the gate insulation film; (c) forming a source region and a drain region in the semiconductor substrate so as to align with the gate electrode; (d) forming a first insulation film over the gate electrode, the source region and the drain region; (e) forming a first plug and a second plug in the first insulating film, wherein the first plug is electrically connected to the source region and the second plug is electrically connected to the drain region; (f) forming a first wire and a second wire over the first insulation film, wherein the first wire is electrically connected to the first plug and the second wire is electrically connected to the second plug; (g) forming a second insulation film over the first insulating film, the first wire and the second wire; (h) forming a third plug and a fourth plug in the second insulation film, wherein the third plug is electrically connected to the first wire and the fourth plug is electrically connected to the second wire; and (i) forming a third wire and a fourth wire over the second insulation film, wherein the third wire is electrically connected to the third plug and the third fourth is electrically connected to the fourth plug, wherein the gate electrode and the first wire are arranged so as to not be overlapped with each other in a planar view, wherein the gate electrode and the second wire are arranged not to be overlapped with each other in a planar view, wherein the gate electrode and an edge of the third wire are arranged to be overlapped with each other in a planar view, and wherein the gate electrode and an edge of the fourth wire are arranged to be overlapped with each other in a planar view.