Performance-driven and gradient-aware dummy insertion for gradient-sensitive array

摘要

The present disclosure relates to an arrangement and a method of performance-aware buffer zone placement for a high-density array of unit cells. A first feature density of the array is measured and maximum variation for a parameter within a unit cell is determined. A look-up table of silicon data is consulted to predict a buffer zone width and gradient value that achieves a variation that is less than the maximum variation for the unit cell. The look-up table contains a suite of silicon test cases of various array and buffer zone geometries, wherein variation of the parameter within a respective test structure is measured and cataloged for the various buffer zone geometries, and is also extrapolated from the suite of silicon test cases. A buffer zone is placed at the border of the array with a width that is less than or equal to the buffer zone width.

主权项

1. A method of assembling a layout comprising:
measuring a first density of gate features or source/drain diffusion features within an array of unit cells with a layout tool comprising hardware; measuring a background density of gate features or source/drain diffusion features within background circuitry, which is arranged outside the array with the layout tool; determining a maximum variation for a parameter of a unit cell of the array as a function of a density gradient between the first density and the background density; consulting a look-up table to predict a buffer zone width that achieves a variation of the parameter that is less than the maximum variation; and forming a buffer zone, comprising a width that is less than or equal to the buffer zone width, between the array and the background circuitry, wherein the buffer zone further comprises a second density, which is less than the first density, and which is greater than the background density.