Optimized mechanism to simplify the circulant shifter and the P/Q kick out for layered LDPC decoder

摘要

A layered LDPC decoder architecture includes a single MUX and a single shifter element for processing an optimized LDPC parity check matrix. The optimized LDPC parity check matrix may be a K×L sub-matrix having zero elements, non-zero elements defined by a circulant matrix or zero matrices, and identity matrixes.

主权项

1. A method for decoding a LDPC encoded signal in a layered architecture, comprising:
bit-shifting, with a computer processor, a first signal based on a delta shift value; selecting, with a computer processor, a signal from the bit-shifted first signal and a second combined signal, wherein the second combined signal is a combination of at least two signals; and storing the selected signal in a ping-pong memory designated for storing some combination of P type messages, Q type messages and log likelihood ratios (LPQ memory).