| 发明名称 |
Programmable logic device data rate booster for digital signal processing |
| 摘要 |
A programmable logic device is provided that includes: a programmable interconnect adapted to route input signals through the device at a system clock rate; and a digital signal processor (DSP) block coupled to the interconnect, the DSP block including: a plurality of input ports; an input register coupled to the multiple input ports and adapted to sequentially register samples of the input signals from the interconnect received at the input ports at a multiple of the system clock rate; and a multiplier adapted to multiply the registered samples at the multiple of the system clock rate to produce an output signal. |
| 申请公布号 |
US8977885(B1) |
申请公布日期 |
2015.03.10 |
| 申请号 |
US201213412408 |
申请日期 |
2012.03.05 |
| 申请人 |
Lattice Semiconductor Corporation |
发明人 |
Hazanchuk Asher |
| 分类号 |
G06F1/04;G06F5/06 |
主分类号 |
G06F1/04 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A programmable logic device, comprising:
a programmable interconnect adapted to route input signals through the device at a system clock rate; and a digital signal processor (DSP) block coupled to the interconnect, the DSP block including:
a plurality of input ports;a multiplexer coupled to the plurality of input ports and adapted to alternately select among the input signals from the interconnect received at the input ports at a multiple of the system clock rate;an input register coupled to the multiplexer and adapted to register samples of the input signals from the multiplexer at the multiple of the system clock rate; anda multiplier adapted to multiply the registered samples at the multiple of the system clock rate to produce an output signal. |
| 地址 |
Hillsboro OR US |
